بسم الله الرحمن الرحيم


Memory terminology, including new and old technology



Array

The area of the RAM that stores the bits. The array consists of rows and columns, with a cell at each intersection that can store a bit. The large rectangular section in the centre of the die where the memory is stored.
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Asynchronous Cache

An SRAM that does not require a clock signal to validate its control signals. About 30% lower in price and performance compared to synchronous cache.
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Auto Refresh

Commonly referred to as CAS before RAS refresh or CE before RE refresh. An internal address counter increments the row address each time the memory controller initiates a CAS before RAS refresh cycle.
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BEDO DRAM

Burst EDO DRAM: a type of EDO DRAM that can process four memory addresses in one burst. Unlike SDRAM, however, BEDO DRAM can only stay synchronised with the CPU clock for short periods (bursts) and it can't keep up with processors whose buses run faster than 66 MHz.
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Burst Mode

Bursting is a rapid data-transfer technique that automatically generates a block of data (a series of consecutive addresses) every time the processor requests a single address. The assumption is that the next data-address the processor will request will be sequential to the previous one. Bursting can be applied both to read operations (from memory) and write operations (to memory).
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Cache Controller

The circuit in control of the interface between the CPU, cache and DRAM (main memory).
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Cache Hit

When the address requested by the CPU is found in cache. Conversely, cache miss is when its not found.
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Cache Memory

A small block of high-speed memory (usually SRAM) located between the CPU and main memory that is used to store frequently requested data and instructions. Properly designed, a cache improves system performance by reducing the need to access the system's slower main memory for every transaction.
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CAS

Column Address Select (or Strobe): a control pin on a DRAM used to latch and activate a column address. The column selected on a DRAM is determined by the data present at the address pins when CAS becomes active. Used with RAS and a row-address to select a bit within the DRAM.
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CELP

A Card Edge Low Profile socket is often used for cache modules.
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Check Bits

Extra data bits provided by a DRAM module to support ECC function. For a 4-byte bus, 7 or 8 check bits are needed to implement ECC, resulting in a total bus width of 39 or 40 bits. On an 8-byte bus, 8 additional bits are required, resulting in a bus width of 72 bits.
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CMOS

Complementary Metal Oxide Semiconductor: a process that uses both N- and P-channel devices in a complimentary fashion to achieve small geometries and low power consumption.
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COAST

Cache On A Stick: another popular design specification for cache modules.
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Column

Part of the memory array. A bit can be stored where a column and a row intersect.
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CompactFlash

CF: a flash memory format introduced by SanDisk Corporation in 1994 which has become widely used for handheld digital devices.
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DDR

Double Data Rate: a memory technology that works by allowing the activation of output operations on the chip to occur on both the rising and falling edge of a clock cycle, thereby providing an effective doubling of the clock frequency without increasing the actual frequency.
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DIMM

Dual In-line Memory Module: a form of chip packaging, designed to meet JEDEC standards, that is rapidly replacing SIMM as the module standard for the PC industry as memory subsystems standardise around an 8-byte data interface. Importantly, and unlike SIMMs, they can be used singly.
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DIP

Dual In-Line Package chip housing with pins on each edge.DQMData mask signal used by SDRAMs to provide byte masking during write operations. There is one DQM signal for every 8 bits of data width.
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DRAM

Dynamic Random Access Memory: the read/write memory used to store data in personal computers. DRAM stores each bit of information in a "cell" composed of a capacitor and a transistor. Because the capacitor in a DRAM cell can hold a charge for only a few milliseconds, DRAM must be continually refreshed in order to retain its data. See also EDO RAM and SRAM.
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DRDRAM

Direct Rambus DRAM: a totally new RAM architecture, complete with bus mastering (the Rambus Channel Master) and a new pathway (the Rambus Channel) between memory devices (the Rambus Channel Slaves). A single Rambus Channel has the potential to reach 500 MBps in burst mode; a 20- fold increase over DRAM.
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EAROM

Electrically Alterable Read-Only Memory.

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ECC

Error Correction Code: a system of scrambling data and recording redundant data in stored data in order to enable the detection of errors that can be corrected by the device’s controller when the data is read. ECC memory can detect up to 4-bit memory errors; only single-bit errors, however, can be corrected. See also CRC.
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ECC optimised

On a SIMM or DIMM, the use of a module addressing architecture that facilitates the use of the memory module by systems with ECC. ECC optimised memory modules do not have byte-write capability.
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EDO DRAM

Extended Data Out Random Access Memory: a form of DRAM that has a two-stage pipeline, which lets the memory controller read data off the chip while it is being reset for the next operation. While similar in performance to synchronous DRAM (SDRAM), it cannot support bus speeds above 66MHz.
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EDRAM

Enhanced Dynamic Random Access Memory: a form of DRAM that boosts performance by placing a small complement of static RAM (SRAM) in each DRAM chip and using the SRAM as a cache. Also known as cached DRAM, or CDRAM.
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EEPROM

Electrically Erasable Programmable Read Only Memory: a special type of read-only memory (ROM) that can be erased and written electrically. EEPROM maintains its contents without power backup and is frequently used for system-board BIOS's.
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EPROM

Erasable Programmable Read Only Memory: an integrated circuit memory chip that can store programs and data in a non-volatile state. These devices can be erased by high-intensity ultraviolet (UV) light and then rewritten, or "reprogrammed", in a manner similar to common DRAM. EPROM chips normally contain UV-permeable quartz windows exposing the chips' internals.
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Flash Memory

Flash memory is a non-volatile memory device that retains its data when the power is removed. The device is similar to EPROM with the exception that it can be electrically erased, whereas an EPROM must be exposed to ultra-violet light to erase. Commonly used in digital cameras.
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FPM DRAM

Fast Page Mode RAM: a timing option that permits several bits of data in a single row on a DRAM to be accessed at an accelerated rate. Fast Page Mode involves selecting multiple column addresses in rapid succession once the row address has been selected.
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HPM

Hyper Page Mode: in DRAM operation, another term for EDO or Extended Data Out.
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Index

The subset of the CPU address bits used to get a specific location within cache.
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Interleave

Generally refers to the arrangement of data in a non-contiguous way to increase performance. When used in the context of hard disk drives, it describes the way in which sectors are arranged on a track. When used in the context of memory subsystems, it refers to the process of taking data bits (singly or in bursts) alternately from two or more memory pages.
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JEDEC

An organisation that establishes standards for memory operation, features, and packaging.
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Keys

Notches in a memory module (DRAM DIMM or SIMM) that prevent them from being plugged into an incompatible system. For example, a DIMM keyed for 3.3V operation cannot be plugged into a socket designed for use with a 5V system.
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Latch

Circuit element that stores a given value on its output until told to store a different value.
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Level 1 Cache

Cache that is closest to the processor: typically located inside the CPU chip. Can be implemented either as a unified cache or as separate sections for instructions and data. Also referred to as primary cache or internal cache.
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Level 2 Cache

Cache that is second closest to the processor; typically located on the system board. Also referred to as secondary cache and external cache.
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Level 3 Cache

Level 3 Cache: a memory reservoir near the processor that boosts performance beyond that possible with traditional two-level cache designs. First seen in early 1999 on AMD's K6-III CPU, a similar system was later used by Intel's 64-bit Itanium processor.
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Memory Bank

A logical unit of memory in a computer, the size of which the CPU determines. For example, a 32-bit CPU requires memory banks that provide 32 bits of information at a time. A bank can consist of one or more memory modules.
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Memory Controller

An essential component in any computer. Its function is to oversee the movement of data into and out of main memory. It also determines what type of data integrity checking, if any, is supported.
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Memory Cycle

Minimum amount of time required for a memory to complete a cycle such as read, write, read/write, or read/modify/write.
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MNOS

Metal Nitride Oxide Semiconductor: the technology used for EAROMs (Electrically Alterable ROMs); not to be confused with NMOS.
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MOS

Metal-Oxide-Semiconductor: layers used to create a semiconductor circuit. A thin insulating layer of oxide is deposited on the surface of the wafer. Then a highly conductive layer of tungsten silicide is placed over the top of the oxide dielectric.
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NMOS

N-channel Metal Oxide Semiconductor: pertains to MOS devices constructed on a P-type substrate in which electrons flow between N-type source and drain contacts. NMOS devices are typically two to three times faster than PMOS devices.
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Non-Volatile Memory

Types of memory that retain their contents when power is turned off. ROMs, PROMs, EPROMs and flash memory are examples. Sometimes the term refers to memory that is inherently volatile, but maintains its content because it is connected to a battery at all times, such as CMOS memory and to storage systems, such as hard disks.
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Page

On a DRAM, the number of bits that can be accessed from one row address. The size of a page is determined by the number of column addresses. For example, a device with 10 column address pins has a page depth of 1024 bits.
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Parity Memory

A common method for ensuring the integrity of data stored in memory in which an additional data bit is generated and added to each data byte. Parity is able to detect only single bit errors reliably but cannot perform any correction. If more than one bit has been corrupted, the parity check may not detect a problem. The most commonly used forms of parity are even parity, odd parity, and checksums.
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Pipeline

In DRAMs and SRAMs, a method for increasing the performance using multistage circuitry to stack or save data while new data is being accessed. The depth of a pipeline varies from product to product. For example, in an EDO DRAM, one bit of data appears on the output while the next bit is being accessed. In some SRAMs, pipelines may contain bits of data or more.
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Pipeline Burst Cache

A type of synchronous cache that uses two techniques to minimise processor wait states - a burst mode that pre-fetches memory contents before they are requested, and pipelining so that one memory value can be accessed in the cache at the same time that another memory value is accessed in DRAM.
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PMOS

P-channel Metal Oxide Semiconductor: pertains to MOS devices constructed on an N-type silicon substrate in which holes flow between source and drain contacts.
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RAM

Random Access Memory: the PC’s primary storage area, used to write, store and retrieve information and program instructions which are then passed to the CPU for processing. The type of RAM used affects performance as the information stored here has to be refreshed many times per second by the processor. Manufacturers are continually coming up with new designs to provide the fastest possible access times at the lowest possible cost.
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RAS

Row Address Select (or Strobe): a control pin on a DRAM used to latch and activate a row address. The row selected on a DRAM is determined by the data present at the address pins when RAS becomes active.
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Refresh

The process used to restore the charge in DRAM memory cells at specified intervals. The required refresh interval is a function of the memory cell design and the semiconductor technology used to manufacture the memory device. There are several refresh schemes that may be used.
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Registered Memory

A type of SDRAM memory that uses registers to hold data for one clock cycle before it is moving it on and in so doing increases the reliability of high-speed data access. Registered memory modules are typically used only in server environments and other mission-critical systems. Registered and unbuffered memory cannot be mixed. the design of the processor’s memory controller dictating which type is required.
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RIMM

A form of chip packaging that is similar to DIMMs to be used with the next generation of Direct DRAM memory subsystems.
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ROM

Read Only Memory: an integrated circuit chip containing programs and data that can be accessed and read but cannot be modified.
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Row

Part of the RAM array; a bit can be stored where a column and a row intersect.
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SDRAM

Synchronous DRAM: a type of DRAM designed to deliver bursts of data at very high speeds using automatic addressing, multiple page interleaving, and a synchronous (or clocked) interface. SDRAM can support bus speeds of up to 100MHz today and will probably support bus speeds of up to 200MHz in the future.
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Secure Digital

SD: a postage stamp size portable flash memory format developed by Toshiba, Sandisk and Panasonic. Content encoded on an SD card may be encrypted, providing copyright protection of intellectual properties. Expected to the industry standard for the warehousing and transfer of digital media including music, still and moving video, talking books, etc.
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SGRAM

Synchronous Graphics RAM: a single ported DRAM designed for high-speed, serial data, and usually used on graphics boards.
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SIMM

Single In-Line Memory Module: On Pentium-class PCs, SIMM-style RAM chips replaced the dual in-line package (DIP) chips, identifiable by two rows of protruding legs, that were popular in the 1980s. They are themselves being replaced by the DIMM module.
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SmartMedia

An ultra-compact flash memory format developed by Toshiba. About the size of CompactFlash, but as thin as a credit card, SmartMedia cards can be plugged into a SmartMedia socket or into a standard Type II PC Card slot with an adapter.
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SOJ

Small Outline J-Lead package: this plastic package, designed for memory chips, is a surface mount package with turned under leads that look like the letter J.
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SRAM

Static Random Access Memory: a form of RAM that retains its data without the constant refreshing that DRAM requires. SRAM is generally preferable to DRAM because it offers faster memory access times, but it is also more expensive to manufacture because it contains more electrical components.
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Strobe

An input that allows parallel data to be entered asynchronously.
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Synchronous Cache

An SRAM that requires a clock signal to validate its control signals. This enables the cache memory to run lockstep with the CPU. Can be either Burst or Pipelined Burst.
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Tag

The subset of the CPU address bits used to compare the tag bits of the cache directory to the main memory address being accessed.
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Tag RAM

Cache is physically divided into two sections. The Tag RAM section stores the Tag address of the location of the data in cache. This section is smaller than the Data RAM section, which stores the actual data or instruction.
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Volatile Memory

Memory that loses its contents when the power is turned off. A computer's main memory, made up of dynamic RAM or static RAM chips, loses its content immediately upon loss of power. Contrast ROM, which is non-volatile memory.
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VRAM

Video Random Access Memory: a dual-ported DRAM designed for graphics and video applications. One port provides data to the CRT, while the other is used for read/write transfers from the graphics controller. See also WRAM.
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WRAM

Windows Random Access Memory: a form of VRAM used exclusively by Matrox Graphics. WRAM has added logic designed to accelerate common video functions such as bit-block transfers and pattern fills. It can substantially speed up certain graphical operations such as video playback and screen animation.
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Write Back

Data written into the cache by the CPU is not written into main memory until that data line in the cache is to be replaced. Also referred to as Copy Back.
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Write Through

A technique for writing data from the CPU simultaneously into the cache and into main memory to assure coherency.